The present invention relates to programmable logic devices. More specifically, the present invention relates to estimation of resource capacitances within a programmable logic device.
Logic devices may be roughly divided into two categories: fixed logic devices and programmable logic devices (PLDs). Fixed logic devices, such as microprocessors and application specific integrated circuits (ASICs), have internal logic fully determined at the end of the design cycle. The design reached at the end of the fixed logic device design cycle is implemented during fabrication into the fixed logic device. This implemented logic may be tested to measure the dynamic power required by the fixed logic device. Dynamic power is the power consumption of the logic device due to the switching of internal nodes and inputs and outputs in an active device. Because all fixed logic devices implementing the same design are identically fabricated, determining the dynamic power used by one fixed logic device provides an estimate of the dynamic power used by all fixed logic devices implementing the same design. As a result, fixed logic devices have a known range of dynamic power usage.
In contrast, the end of the design cycle of a PLD, such as a field programmable gate array (FPGA), occurs after the PLD is fabricated. Thus, while the programmable logic is implemented in the PLD at fabrication, a particular internal configuration logic of these PLDs is determined by a user after PLD fabrication. The internal logic of a PLD is defined by creating connections between the internal resources of the PLD (e.g. interconnect lines, look-up tables, and flip-flops). Additionally, with the advent of reprogrammability, the same PLD may have many different implemented designs at different times. Because different designs may be implemented in the logic within a PLD, the dynamic power required by the PLD may not be measured until the particular design to be implemented is defined and implemented in the PLD. Note that while it is possible to measure the power used by a particular design by standard means after a design is implemented within a PLD, it would be useful to obtain an estimation of power used by a particular design prior to the implementation of the design in the PLD. To this end, it would be desirable to provide a generic method that captures all the internal capacitances of the resources within a PLD for use with a tool to estimate power.
Power in a CMOS logic device is measured by the following equation:
P=C*V2*fxe2x80x83xe2x80x83(Equation 1)
where C is the capacitance of all of the resources within the logic device, V is the operating voltage of the logic device, and f is the operating clock frequency of the logic device.
In PLDS, a user may select different resources to form different designs, in addition to selecting the operating clock frequency for the design. For example, a first user design, created from a first set of PLD resources in a particular PLD may consume 10W of power while a second user design created from a second set of resources in that PLD may consume 20W of power. Thus, the power used by a PLD for a given design depends on the resources used by that design. Therefore, Equation 1 (the power equation) is modified for PLDs to measure power used by each resource, as shown by the following equation:                     P        =                              ∑            i                          xe2x80x83                                ⁢                      xe2x80x83                    ⁢                                    C              i                        *                          V              2                        *            f                                              (                  Equation          ⁢                      xe2x80x83                    ⁢          2                )            
where Ci is the capacitance of the ith resource within the PLD, V is the operating voltage of the PLD, and f is the operating clock frequency of the PLD. Both the operating voltage and the operating clock frequency are determined by the user. Thus, only the capacitance of each resource within the PLD is unknown.
It would be desirable to provide a power estimating tool to generate the power analysis for a particular design implemented in a PLD. For example, a power estimator may be a piece of software which takes as parameters a design definition file (e.g. a .ncd file) and user parameters (e.g. operating frequency of the design) and in return provides an estimate of the power consumption of the PLD implementing that design. However, to estimate power in this way using Equation 2, the capacitance of each resource on the PLD used in the design must be known. The presence of PLD device packaging as well as the small scale of the silicon die precludes the direct measurement of the capacitance of individual PLD resources. Thus, a tool estimating power in a PLD according to Equation 2 first requires a capacitance of each resource used for a particular design within the PLD. Thus, it would be desirable to provide a method for estimating capacitances within a PLD to serve as a basis for such a power estimating tool.
Accordingly, the present invention provides a method of estimating a capacitance for each quantifiable resource in a programmable logic device (PLD). Note that because some resources in a PLD are always instantiated together, these co-instantiated resources are grouped as one resource for the purpose of determining capacitance. The current drawn by a reference circuit implemented in the PLD is measured at a given frequency and operating voltage. The capacitance of the reference circuit is calculated using the current drawn, the frequency, and the operating voltage. The current drawn by a resource load coupled to the reference circuit is measured at the given frequency and operating voltage. The capacitance of the resource load coupled to the reference circuit is calculated using the current drawn, the frequency, and the operating voltage. The capacitance of the resource load may be calculated by subtracting the capacitance of the reference circuit from the capacitance of the resource load coupled to the reference circuit. Each resource within the PLD may be sequentially used as a resource load, thereby determining the capacitance of each resource within the PLD as described above.
To ensure that the currents drawn by the reference circuit and the resource load coupled to the reference circuit are sufficiently large enough to measure, multiple identical reference circuits may be implemented in the PLD. Using multiple identical reference circuits, a proportionally larger total current is drawn. As a result, noise margins and resolution are improved in the power calculation. The total current drawn by all of the reference circuits, along with the frequency and the operating voltage, is used to determine a total reference circuit capacitance. This total reference circuit capacitance is divided by the number of reference circuits to estimate a capacitance for each individual reference circuit. Similarly, multiple identical loads are coupled to the reference circuit, respectively. The total current drawn by all of the reference circuits plus the loads (i.e., loaded reference circuit) is measured and used to determine a total loaded reference circuit capacitance. The capacitance of one loaded reference circuit is estimated by subtracting the total reference circuit capacitance from the total loaded reference circuit capacitance and dividing by the number of reference circuits.